1. Field of the Invention
This invention relates to design structures for integrated circuits, and more particularly to design structures for facilitating engineering changes in integrated circuits.
2. Description of the Related Art
Continuing improvements in integrated circuit (IC) technology have enabled the development of increasingly complex logic circuitry on smaller and smaller areas of silicon. This has led to rapid increases in IC function and immense improvements in performance. In general, the fabrication of complex ICs involves forming components such as transistors, capacitors, or the like on a silicon substrate. Metal layers may then be applied to the substrate to create conductive interconnections between the components. The placement and routing of these components and interconnections is typically a time-consuming and laborious process that may take weeks or even months to complete.
When designing large ICs (e.g., ASICs), engineering change orders (ECOs) are often performed to make small logic or circuit modifications to already completed (or almost completed) IC designs. Because the placement and routing of IC components and interconnections in such designs is usually very dense and congested (to achieve small IC size), implementing these ECOs can be a time-consuming and problematic process. From distilling down the minimal change in a netlist (when the change was made to RTL) to rewiring gates on an existing placement, such modifications are almost always time-consuming and complicated and do not lend themselves to automation.
In view of the foregoing, what is needed is a method and design structure for simplifying engineering changes to ICs, thereby reducing the cost and time needed to implement such changes. Further needed is a design structure that has a consistent and identifiable structure and is able to provide different logical operations using a simple rewiring process. Further needed is a method and design structure to implement engineering changes in an automated manner.